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MP3213 – 700KHZ/1.3MHZ BOOST CONVERTER WITH A 3.5A SWITCH
MP3213 Rev. 1.1
5/12/2006
www.MonolithicPower.com
8
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
2006 MPS. All Rights Reserved.
Compensation
The output of the transconductance error
amplifier (COMP) is used to compensate the
regulation control system. The system uses two
poles and one zero to stabilize the control loop.
The poles are f
P1
set by the output capacitor C2
and load resistance and f
P2
set by the
compensation capacitor C3. The zero f
Z1
is set
by the compensation capacitor C3 and the
compensation
resistor
determined by the equations:
R3.
These
are
LOAD
1
P
R
C2
×
1
×
f
π
=
VEA
EA
2
P
A
C3
×
2
G
f
×
π
×
=
R3
×
C3
×
2
1
f
1
Z
π
×
=
Where R
LOAD
is the load resistance, G
EA
is the
error amplifier transconductance, and A
VEA
is
the error amplifier voltage gain.
The DC loop gain is:
2
LOAD
OUT
V
FB
IN
VEA
VDC
V
R
V
A
5
A
×
×
×
×
=
Where V
FB
is the feedback regulation threshold.
There is also a right-half-plane zero (f
RHPZ
) that
exists in continuous conduction mode (inductor
current does not drop to zero on each cycle)
step-up converters. The frequency of the right
half plane zero is:
2
2
OUT
V
LOAD
IN
π
RHPZ
L
2
R
×
V
×
f
×
×
=
Table
compensation components for different input
voltage, output voltage and capacitance of most
frequently used output ceramic capacitors.
Ceramic capacitors have extremely low ESR,
therefore the second compensation capacitor
(from COMP to GND) is not required.
1
lists
generally
recommended
Table 1—Component Selection
V
IN
(V)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
5
5
5
5
5
5
5
5
5
12
12
12
12
12
12
V
OUT
(V)
8
8
8
12
12
12
18
18
18
8
8
8
12
12
12
18
18
18
15
15
15
18
18
18
C2
(μF)
4.7
10
22
4.7
10
22
4.7
10
22
4.7
10
22
4.7
10
22
4.7
10
22
4.7
10
22
4.7
10
22
R3
(k
)
10
10
10
15
15
15
20
20
30
10
10
15
15
15
20
20
20
30
10
10
15
5.1
5.1
15
C3
(nF)
2.2
2.2
2.2
1
1
2.2
1
1
2.2
4.7
4.7
1
2.2
2.2
1
1
1
1
2.2
2.2
1
2.2
2.2
1
For faster control loop and better transient
response, set the capacitor C3 to the
recommended value in Table 1. Then slowly
increase the resistor R3 and check the load
step response on a bench to make sure the
ringing and overshoot on the output voltage at
the edge of the load steps is minimal. Finally,
the compensation needs to be checked by
calculating the DC loop gain and the crossover
frequency. The crossover frequency where the
loop gain drops to 0dB or a gain of 1 can be
obtained visually by placing a –20dB/decade
slope at each pole, and a +20dB/decade slope
at each zero. The crossover frequency should
be at least one decade below the frequency of
the right-half-plane zero at maximum output
load current to obtain high enough phase
margin for stability.
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